1. Field of the Invention
The present invention relates to a multiport memory having a plurality of ports and to a control method of a multiport memory.
2. Description of the Related Art
The related art includes two-port memory equipped with a memory array configured from memory cells having two ports. In a two-port memory, simultaneous data reading from the same memory cell is enabled by the two ports (for example, see IDT 70T 3539M data sheet, Integrated Device Technology, Inc., May, 2004). Two-port DRAM having two ports also exists (for example, see JP-A-2007-35039).
The inventors of the present application previously investigated data communication methods between the ports of two-port SRAM.
In various information processing devices, two-port SRAM was used in data communication between the plurality of LSIs that make up an information processing device. A data communication method between the A-port (A-PRT) and B-port (B-PRT) in a two-port SRAM is next shown. INTA and INTB are signals corresponding to each port for reporting that information has been written to a Mail Box.
(1) A-PRT: The commencement of data writing from A-PRT and the start address are written to the Mail Box. INTB becomes “LOW.”
(2) B-PRT: The transition of INTB to “LOW” reports the writing of information to the Mail Box. The information in the Mail Box is then read from B-PRT, whereby the writing of data from A-PRT and the start address are known. INTB becomes “HIGH.”
(3) A-PRT: The data are written from A-PRT, and when data writing ends, completion of data writing and the final address are written to the Mail Box. INTB becomes “LOW.”
(4) B-PRT: The writing of information to the Mail Box is known from the transition of INTB to “LOW.” The information in the Mail Box is then read from B-PRT, data writing from A-PRT ends, and the end address of this data writing is further known. INTB becomes “High.”
(5) B-PRT: The commencement of data reading from B-PRT and the start address are written to the Mail Box. INTA becomes “Low.”
(6) A-PRT: The writing of information to the Mail Box is known from the transition of INTA to “Low.” The information in the Mail Box is then read from A-PRT, and reading of data from B-PRT and the start address are known. INTA become “High.”
(7) B-PRT: Data are read from B-PRT, and when completed, the completion of data reading and the end address are written to the Mail Box. INTA becomes “Low.”
(8) A-PRT: The writing of data to the Mail Box is known from the transition of INTA to “Low.” The information in the Mail Box is then read from A-PRT, the reading of data from B-PRT is completed, and further, the end address is known. INTA becomes “High.”
In this way, writing and reading are carried out to and from a Mail Box in data communication between the A-port and the B-port of a two-port SRAM. Data communication is carried out by the so-called handshake method.
Data communication between A-port and B-port is thus delayed and obviously cannot cope with the higher speeds of an information processing system.